1. Field of the Invention
The present invention relates to telecommunications, and more particularly, to a subscriber bus interface in a telecommunications system.
2. Background
The telecommunications industry has developed schemes for transmitting telephony signals in digital formats, for example, in the form of time division multiplexed (TDM) signals for transmission over a physical layer interface, such as a conventional subscriber bus interface (SBI) in a synchronous optical network (SONET). The SONET uses an industry-standard framed transmission format in which communications signals in the form of data bits are carried within SONET frames each having a duration of 125 xcexcs. Each SONET frame is divided into a plurality of time slots for carrying payload data bits representing digitized telephony signals for conventional telephone services.
An example of a conventional telephone service is a plain old telephone service (POTS), which uses an industry-standard digital format that is known to a person skilled in the art. Payload data bits representing the telephony signals can be carried within a plurality of conventional Digital Signal 0 (DS0) cells which are assigned to the time slots within the SONET frames. An industry-standard DS0 cell, which is known to a person skilled in the art, is transmitted over a conventional SBI at a data rate of 64 kilobits per second (Kbps) per channel.
In a conventional channel bank for transporting POTS traffic, a conventional SBI typically operates at a fixed data rate of 2.048 megabits per second (Mbps) for transporting DS0 cells. At a data rate of 2.048 Mbps, the conventional SBI supports 24 DS0 channels with associated signaling, timing and data link cells. Although this data rate is adequate for POTS traffic using low-density quadruple or octal POTS channel cards and single T1 channel cards, a conventional SBI running at the fixed data rate of 2.048 Mbps is incapable of interfacing with higher-density channel cards such as quadruple T1 channel cards and asynchronous transfer mode (ATM) optical line units (AOLUS) which operate at higher data rates.
Therefore, there is a need for a subscriber bus which is capable of operating at data rates higher than the fixed data rate of 2.048 Mbps provided by a conventional fixed-rate subscriber bus interface. Furthermore, it is desirable that a subscriber bus be able to support multiple data rates for compatibility with a variety of high density channel cards, as well as the standard data rate of 2.048 Mbps for compatibility with existing channel units, including low-density quadruple or octal POTS channel cards and single T1 channel cards.
In accordance with the present invention, a variable rate subscriber bus roughly comprises:
(a) a clock channel capable of transferring a clock signal at a predetermined clock frequency; and
(b) a plurality of Digital Signal 0 (DS0) channels capable of transferring a plurality of DS0 cells at a selected one of a plurality of predetermined data rates for transferring the DS0 cells, the predetermined data rates including a basic data rate and at least one higher data rate, each of the DS0 cells carrying a plurality of data bits which are transferred at the selected data rate, the clock signal providing a timing reference to the data bits at any one of the predetermined data rates selected for transferring the DS0 cells.
In an embodiment, the subscriber bus further comprises a frame synchronization channel capable of transferring a timing pulse defining a synchronous optical network (SONET) frame. In a further embodiment, the DS0 cells are synchronized at a frame rate of 8 KHz based upon the SONET frame which has a duration of 125 xcexcs. In another embodiment, the subscriber bus further comprises a superframe synchronization channel capable of transferring a timing pulse defining a subscriber bus superframe for synchronizing the DS0 cells. In a further embodiment, the DS0 cells are synchronized at a frame rate of 1 KHz based upon the subscriber bus superframe, which consists of 8 SONET frames and has a duration of 1 ms.
In an embodiment, the subscriber bus according to the present invention is capable of supporting the basic data rate, which is the standard data rate of 2.048 Mbps for compatibility with conventional low-density channel cards, as well as a plurality of higher data rates for compatibility with a variety of higher-density channel cards. In an embodiment, each of the higher data rates is an integral multiple of the basic data rate. In a further embodiment, the integral multiple is an integral power of two. In an embodiment, the predetermined data rates which the subscriber bus according to the present invention is capable of supporting comprises the basic data rate of 2.048 Mbps and the higher data rates of 4.096 Mbps, 8.192 Mbps and 16.384 Mbps. In an embodiment, the predetermined clock frequency is 4.096 MHz to provide a timing reference for the DS0 cells at any one of the predetermined data rates.
In an embodiment in which the DS0 cells are transferred at the basic data rate of 2.048 Mbps, eight odd time slots and eight even time slots are provided within each of the DS0 cells. The odd and even time slots are interleaved with each other. In an embodiment, eight data bits of a data byte are assigned only to the odd time slots within each of the DS0 cells.
In an embodiment in which the subscriber bus according to the present invention operates at a data rate of 4.096 Mbps, sixteen time slots are provided within each of the DS0 cells. In this embodiment, two data bytes each consisting of eight data bits are assigned to each of the DS0 cells. In an embodiment, a first one of the two data bytes is assigned to a first half of the sixteen time slots, and a second one of the two data bytes is assigned to a second half of the sixteen time slots subsequent in sequence to the first half.
In an embodiment in which the subscriber bus according to the present invention operates at a data rate of 8.192 Mbps, thirty-two time slots are provided within each of the DS0 cells. In this embodiment, four data bytes each consisting of eight data bits are assigned to each of the DS0 cells. In an embodiment, the four data bytes are byte-interleaved with each other within each of the DS0 cells.
In an embodiment in which the subscriber bus according to the present invention operates at a data rate of 16.384 Mbps, sixty-four time slots are provided within each of the DS0 cells. In this embodiment, eight data bytes each consisting of eight data bits are assigned to each of the DS0 cells. In an embodiment, the eight data bytes are byte-interleaved with each other within each of the DS0 cells.
In an embodiment, the SONET frame comprises a first cell slot and a first set of three DS0 cells immediately following the first cell slot. In a further embodiment, the SONET frame further comprises a signaling cell immediately following the first set of three DS0 cells and a second set of three DS0 cells immediately following the signaling cell. In yet a further embodiment, the SONET frame further comprises a framing cell immediately following the second set of three DS0 cells.
In an embodiment in which the cell slots in the SONET frame carry standard DS0 cells, the first cell slot comprises a reserved slot. In an alternate embodiment in which the cell slots assigned to carry DS0 cells in the SONET frame carry T1 cells, the first cell slot in the SONET frame comprises a T1 protect state slot. Because a T1 cell is simply a concatenated DS0 cell, the cell format for the variable rate subscriber bus according to the present invention is also applicable to the transferring of T1 cells over the variable rate subscriber bus at any one of the selectable data rates.
The present invention also provides a method of data transmission over a variable rate subscriber bus. The method roughly comprises the steps of:
(a) providing a DS0 cell;
(b) providing a clock signal at a predetermined clock frequency;
(c) providing a plurality of predetermined data rates for the subscriber bus, the predetermined data rates including a basic data rate and at least one higher data rate;
(d) selecting one of the predetermined data rates as a selected data rate for transmitting the data; and
(e) assigning a plurality of data bits to the DS0 cell in dependence upon the selected data rate.
In an embodiment, the method according to the present invention further comprises the step of providing a SONET frame for synchronizing the DS0 cell. In a further embodiment, the method comprises the step of synchronizing a plurality of DS0 cells at a frame rate of 8 KHz based upon the SONET frame which has a duration of 125 xcexcs. In another embodiment, the method according to the present invention further comprises the step of providing a subscriber bus superframe for synchronizing the DS0 cells. In a further embodiment, the DS0 cells are synchronized at a frame rate of 1 KHz based upon the subscriber bus superframe which consists of 8 SONET frames and has a duration 1 ms.
In an embodiment, the predetermined data rates include the basic data rate and a plurality of higher data rates, each of the higher data rates being an integral multiple of the basic data rate. In a further embodiment, the integral multiple is an integral power of two. In an embodiment, the predetermined data rates include the basic data rate of 2.048 Mbps for supporting conventional low-density channel cards and the higher data rates of 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps for supporting higher-density channel cards. In an embodiment, the predetermined clock frequency is 4.096 MHz to provide a timing reference for DS0 cells at any one of the predetermined data rates selected for the variable rate subscriber bus.
In an embodiment in which the DS0 cell is transmitted at the basic data rate of 2.048 Mbps, the method according to the present invention further comprises the step of providing eight odd time slots and eight even time slots within the DS0 cell, the odd and even time slots interleaved with each other. In an embodiment, the method further comprises the step of assigning a data byte consisting of eight data bits only to the odd time slots within the DS0 cell.
In an embodiment in which the DS0 cell is transmitted at a data rate of 4.096 Mbps, the method according to the present invention further comprises the step of providing sixteen time slots within the DS0 cell. Two data bytes each consisting of eight data bits are assigned to the DS0 cell. In an embodiment, a first one of the data bytes is assigned to a first half of the sixteen time slots and a second one of the data bytes is assigned to a second half of the sixteen time slots subsequent in sequence to the first half.
In an embodiment in which the DS0 cell is transmitted at a data rate of 8.192 Mbps, the method according to the present invention further comprises the step of providing thirty-two time slots within the DS0 cell. Four data bytes each consisting of eight data bits are assigned to the DS0 cell. In an embodiment, the method further comprises the step of byte-interleaving the four data bytes within the DS0 cell.
In an embodiment in which the DS0 cell is transmitted at a data rate of 16.384 Mbps, the method according to the present invention further comprises the step of providing sixty-four time slots within the DS0 cell. In this embodiment, eight data bytes each consisting of eight data bits are assigned to the DS0 cell. In an embodiment, the method further comprises the step of byte-interleaving the eight data bytes within the DS0 cell.
In an embodiment, the method according to the present invention further comprises the steps of providing a SONET frame, dividing the SONET frame into a plurality of cell slots comprising a first cell slot and a plurality of subsequent cell slots in temporal sequence, and assigning a first set of three DS0 cells to three of the cell slots immediately following the first cell slot. In a further embodiment, the method according to the present invention further comprises the steps of assigning a signaling cell to a fifth one of the cell slots immediately following the first set of three DS0 cells and assigning a second set of three DS0 cells to three of the cell slots immediately following the signaling cell.
In a further embodiment, the method according to the present invention further comprises the step of assigning a framing cell to a ninth one of the cell slots immediately following the second set of three DS0 cells. In an embodiment in which standard DS0 cells are assigned to the SONET frame, the first cell slot comprises a reserved slot. In an alternate embodiment in which the variable rate subscriber bus is capable of supporting a plurality of T1 channels, the SONET frame comprises a plurality of T1 cells, which are concatenated DS0 cells. In this embodiment, the first cell slot comprises a T1 protect state slot. In an embodiment, three T1 cells are assigned to three of the cell slots immediately following the T1 protect state slot.
Advantageously, the variable rate subscriber bus according to the present invention is capable of supporting POTS traffic or T1 traffic at multiple data rates. The subscriber bus according to the present invention is capable of transporting POTS or T1 traffic at higher data rates for compatibility with higher-density channel cards, such as quadruple T1 channel cards or asynchronous transfer mode (ATM) optical line units (AOLUs). Furthermore, the subscriber bus according to the present invention is also capable of supporting POTS or T1 traffic at the basic data rate of 2.048 Mbps for compatibility with existing conventional channel cards, such as low-density quadruple or octal POTS channel cards or single T1 channel cards.